View M95M02-DRCS6TPK_8309371.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. september 2014 docid18203 rev 9 1/43 m95m02-dr 2-mbit serial spi bus eeprom datasheet - production data features ? compatible with the serial peripheral interface (spi) bus ? memory array ? 2 mb (256 kbytes) of eeprom ? page size: 256 bytes ? write ? byte write within 10 ms ? page write within 10 ms ? additional write lockable page (identification page) ? write protect: quarter, half or whole memory array ? clock frequency: 5 mhz ? single supply voltage: 1.8 v to 5.5 v ? operating temperature range: from -40c up to +85c ? enhanced esd protection ? more than 4 million write cycles ? more than 200-year data retention ? packages ? rohs compliant and halogen-free (ecopack ? ) so8n (mn) 150 mil width wlcsp (cs) www.st.com
contents m95m02-dr 2/43 docid18203 rev 9 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.2 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid18203 rev 9 3/43 m95m02-dr contents 3 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6.1 cycling with error correction code (ecc) . . . . . . . . . . . . . . . . . . . . . . 25 6.7 read identification page (available on ly in m95m02-d devices) . . . . . . . 26 6.8 write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.9 read lock status (available only in m 95m02-d devices) . . . . . . . . . . . . 28 6.10 lock id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of tables m95m02-dr 4/43 docid18203 rev 9 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. significant bits within the address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. operating conditions (m95m02-dr, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. so8n ? 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 37 table 16. m95m02-drcs6tp/k, wlcsp package mechanical da ta . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
docid18203 rev 9 5/43 m95m02-dr list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections (bump side view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 9. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 23. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 37 figure 24. m95m02-drcs6tp/k, wlcsp standard packa ge outline, bump side view . . . . . . . . . . . 38 figure 25. wlcsp 8-bump wafer lenght chip-scale reco mmended land pattern . . . . . . . . . . . . . . . . 39
description m95m02-dr 6/43 docid18203 rev 9 1 description the m95m02 devices are elec trically erasable progra mmable memories (eeproms) organized as 262144 x 8 bits, accessed through the spi bus. the m95m02 can operate with a supply range from 1.8 v to 5.5 v. these devices are guaranteed over the -40 c/+85 c temperature range. the m95m02-dr offers an additional pa ge, named the identification page (256 bytes). the identification page can be used to store se nsitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram the spi bus signals are c, d and q, as shown in figure 1 and table 1 . the device is selected when chip select ( s ) is driven low. communications with the device can be interrupted when the hold is driven low. table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input hold hold input v cc supply voltage - v ss ground - !)# 3 6 ## -xxx (/,$ 6 33 7 1 # $
docid18203 rev 9 7/43 m95m02-dr description 42 figure 2. 8-pin package connections (top view) 1. see section 10: package mechanical data for package dimensions, and how to identify pin-1. figure 3. wlcsp connections (bump side view) 1. see section 10: package mechanical data for package dimensions, and how to identify pin-1. $ 6 33 # (/,$ 1 36 ## 7 !)$ -xxx 069 6 4 9 66 ' & +2/' 9 && :
memory organization m95m02-dr 8/43 docid18203 rev 9 2 memory organization the memory is organized as shown in the following figure. figure 4. block diagram 069 ,k> ^ t }v??}oo}p] ,]pz}o?p pv??}? /lk?z](??p]??? ????p]??? v}v?? ? ?p]??? ?p y}? z}? y ^]}(?z z}vo? wzkd ? ^??? ?p]??? /v?](]?]}v?p le l?
docid18203 rev 9 9/43 m95m02-dr signal description 42 3 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in section 9: dc and ac parameters ). these signals are described next. 3.1 serial data output (q) this output signal is used to transfer data seria lly out of the device. data is shifted out on the falling edge of serial clock (c). 3.2 serial data input (d) this input signal is used to transfer data seri ally into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 3.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) change from the falling edge of serial clock (c). 3.4 chip select (s ) when this input signal is high, the device is de selected and serial data output (q) is at high impedance. the device is in the standby power mode, unless an internal write cycle is in progress. driving chip select ( s ) low selects the device, plac ing it in the active power mode. after power-up, a falling e dge on chip select ( s ) is required prior to the start of any instruction. 3.5 hold (hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be sele cted, with chip select ( s ) driven low.
signal description m95m02-dr 10/43 docid18203 rev 9 3.6 write protect (w ) the main purpose of this input signal is to fr eeze the size of the area of memory that is protected against write instructions (as specifi ed by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write instructions. 3.7 v cc supply voltage v cc is the supply voltage. 3.8 v ss ground v ss is the reference for all signals, including the v cc supply voltage.
docid18203 rev 9 11/43 m95m02-dr connecting to the spi bus 42 4 connecting to the spi bus all instructions, addresses and input data bytes ar e shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select ( s ) goes low. all output data bytes are shifted out of the devi ce, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c ) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 5. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 5 shows an example of three memory devices connected to an spi bus master. only one memory device is selected at a time, so on ly one memory device drives the serial data output (q) line at a time. the other memory devices are high impedance. the pull-up resistor r (represented in figure 5 ) ensures that a device is not selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may leav e all spi bus lines in high impedance at the same time (for example, if the bus master is re set during the transmission of an instruction), the clock line (c) must be connected to an ex ternal pull-down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high): this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. the typical value of r is 100 k . ai12836b spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r
connecting to the spi bus m95m02-dr 12/43 docid18203 rev 9 4.1 spi modes these devices can be driven by a microcontrolle r with its spi peripheral running in either of the following two modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 6 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 6. spi modes supported !)" # -3" #0(! $ #0/, 1 # -3"
docid18203 rev 9 13/43 m95m02-dr operating features 42 5 operating features 5.1 supply voltage (v cc ) 5.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 9: dc and ac parameters ). this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss device pins. 5.1.2 device reset in order to prevent erroneous instruction dec oding and inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until vcc reaches t he por threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 9: dc and ac parameters ). at power-up, when v cc passes over the por threshold, th e device is reset and is in the following state: ? in standby power mode, ? deselected, ? status register values: ? the write enable latch (wel) bit is reset to 0. ? the write in progress (wip) bit is reset to 0. ? the srwd, bp1 and bp0 bits remain unchanged (non-volatile bits). it is important to note that the device must not be accessed until v cc reaches a valid and stable level within the specified [v cc (min), v cc (max)] range, as defined under operating conditions in section 9: dc and ac parameters . 5.1.3 power-up conditions when the power supply is turned on, v cc rises continuously from v ss to v cc . during this time, the chip select ( s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 5 ). in addition, the chip select ( s ) input offers a built-in safety feature, as the s input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first be en detected on chip select ( s ). this ensures that chip select ( s ) must have been high, prior to going low to start the first operation. the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters , and the rise time must not vary faster than 1 v/s.
operating features m95m02-dr 14/43 docid18203 rev 9 5.1.4 power-down during power-down (continuous decrease of the v cc supply voltage below the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters ), the device must be: ? deselected (chip select s should be allowe d to follow the voltage applied on v cc ), ? in standby power mode (there should not be any internal write cycle in progress). 5.2 active power and standby power modes when chip select ( s ) is low, the device is selected, and in the active power mode. the device consumes i cc . when chip select ( s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes into the st andby power mode, and the device consumption drops to i cc1 , as specified in dc characteristics (see section 9: dc and ac parameters ). 5.3 hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. to enter the hold condition, the device must be selected, with chip select ( s ) low. during the hold condition, the serial data ou tput (q) is high impedance, and the serial data input (d) and the serial clock (c) are don?t care. normally, the device is kept selected for th e whole duration of the hold condition. deselecting the device while it is in the hold condition has the effect of resetting the state of the device, and this mechanism can be used if required to reset any processes that had been in progress. (a) (b) figure 7. hold condition activation a. this resets the internal logic, except the wel and wip bits of the status register. b. in the specific case where the device has shifted in a write command (inst + address + data bytes, each data byte being exactly 8 bits), deselec ting the device also triggers the write cycle of this decoded command. dl( f +2/' +rog frqglwlrq +rog frqglwlrq
docid18203 rev 9 15/43 m95m02-dr operating features 42 the hold condition starts when the hold (hold) signal is dr iven low when serial clock (c) is already low (as shown in figure 7 ). figure 7 also shows what happens if the rising an d falling edges are not timed to coincide with serial clock (c) being low. 5.4 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.3: read status register (rdsr) for a detailed description of t he status register bits. 5.5 data protection and protocol control the device features the following data protection mechanisms: ? before accepting the execution of the write and write status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. ? the block protect (bp1, bp0) bits in the status register are used to configure part of the memory as read-only. ? the write protect (w ) signal is used to protect the block protect (bp1, bp0) bits in the status register. for any instruction to be accept ed, and executed, chip select ( s ) must be driven high after the rising edge of serial clock (c) for the last bi t of the instruction, and before the next rising edge of serial clock (c). two points should be noted in the previous sentence: ? the ?last bit of the instruction? can be the eigh th bit of the instruction code, or the eighth bit of a data byte, depending on the instru ction (except for read status register (rdsr) and read (read) instructions). ? the ?next rising edge of serial clock (c )? might (or might not) be the next bus transaction for some other device on the spi bus. table 2. write-protected block size status register bits protected block protected array addresses bp1 bp0 0 0 none none 0 1 upper quarter 30000h - 3fffh 1 0 upper half 20000h - 3fffh 1 1 whole memory 00000h - 3fffh
instructions m95m02-dr 16/43 docid18203 rev 9 6 instructions each command is composed of bytes (msbit tran smitted first), initiate d with the instruction byte, as summarized in table 3 . if an invalid instruction is sent (one not contained in table 3 ), the device automatically enters a wait state until deselected. for read and write commands to memory array and identification page, the address is defined by two bytes as explained in table 4 . table 3. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 rdid read identification page 1000 0011 wrid write identification page 1000 0010 rdls reads the identification page lock status 1000 0011 lid locks the identific ation page in read -only mode 1000 0010 table 4. significant bits within the address bytes (1) (2) 1. a: significant address bit 2. x: bit is don?t care instruction upper address byte b23 b22 ... b17 b16 middle address byte b15 b14 ... b10 b9 b8 lower address byte b7 b6 ... b1 b0 read or write x x . . . a17 a16 a15 a1 4 . . . a10 a9 a8 a7 a6 . . . a1 a0 rdid or wrid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a7 a6 . . . a1 a0 rdls or lid 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
docid18203 rev 9 17/43 m95m02-dr instructions 42 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write a nd wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 8 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select ( s ) being driven high. figure 8. write enable (wren) sequence # $ !)e 3 1 (igh)mpedance )nstruction
instructions m95m02-dr 18/43 docid18203 rev 9 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 9 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait st ate. it waits for a the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion. figure 9. write disable (wrdi) sequence $,g & ' 6 4 +ljk,pshgdqfh ,qvwuxfwlrq
docid18203 rev 9 19/43 m95m02-dr instructions 42 6.3 read status register (rdsr) the read status register (rdsr) instruction is used to read the status register. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 10 . figure 10. read status register (rdsr) sequence the status and control bits of th e status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cy cle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the internal write enable latch is reset, and no write or writ e status register instruction is accepted. the wel bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrs r) instruction completion ? write (write) instruction completion 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non volat ile. they define the size of the area to be software-protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 2 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. # $ 3 )nstruction !)% 1 3tatus2egister/ut (igh)mpedance -3" 3tatus2egister/ut -3"
instructions m95m02-dr 20/43 docid18203 rev 9 6.3.4 srwd bit the status register write disable (srwd) bi t is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal enable the device to be put in the ha rdware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect ( w ) is driven low). in this mode, the non-volatile bits of the status re gister (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instru ction is no longer accepted for execution. table 5. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
docid18203 rev 9 21/43 m95m02-dr instructions 42 6.4 write status register (wrsr) the write status register (wrs r) instruction is used to wr ite new values to the status register. before it can be accepted, a writ e enable (wren) instruction must have been previously executed. the write status register (wrsr) instruct ion is entered by driving chip select ( s ) low, followed by the instruction code, the data byte on serial data input (d) and chip select ( s ) driven high. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and befo re the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. the instruction sequence is shown in figure 11 . figure 11. write status register (wrsr) sequence driving the chip select ( s ) signal high at a byte boundary of the input data triggers the self- timed write cycle that takes t w to complete (as specified in ac tables under section 9: dc and ac parameters ). while the write status register cycle is in pr ogress, the status register may still be read to check the value of the write in progress (wip) bit: the wip bit is 1 during the self-timed write cycle t w , and 0 when the write cycle is complete. the wel bit (write enable latch) is also reset at the end of the write cycle t w . the write status register (wrsr) instruction enables the user to change the values of the bp1, bp0 and srwd bits: ? the block protect (bp1, bp0) bits define the si ze of the area that is to be treated as read-only, as defined in table 2 . ? the srwd (status register write disable) bit, in accordance with the signal read on the write protect pin (w ), enables the user to set or reset the write protection mode of the status register itself, as defined in table 6 . when in write-protected mode, the write status register (wrsr) instruction is not executed. the contents of the srwd and bp1, bp0 bits are updated after the completion of the wrsr instruction, including the t w write cycle. the write status register (wrsr) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. bits b6, b5, b4 are always read as 0. # $ !)d 3 1 (igh)mpedance )nstruction 3tatus 2egister)n -3"
instructions m95m02-dr 22/43 docid18203 rev 9 the protection features of the device are summarized in table 6 . when the status register write disable (srwd) bit in the status register is 0 (its initial delivery state), it is possible to write to the status register (provided that the wel bit has previously been set by a wren instruction), regardless of the logic level applied on the write protect ( w ) input pin. when the status register write disable (srwd) bi t in the status register is set to 1, two cases should be considered, depending on the state of the write protect ( w ) input pin: ? if write protect (w ) is driven high, it is possible to write to the status register (provided that the wel bit has previously be en set by a wren instruction). ? if write protect (w ) is driven low, it is not possible to write to the status register even if the wel bit has previously been set by a wren instruction. (attempts to write to the status register are rejected, and are not a ccepted for execution). as a consequence, all the data bytes in the memory area, which are software-protected (spm) by the block protect (bp1, bp0) bits in the status register, are also hardware-protected against data modification. regardless of the order of the two events, the hardware-protected mode (hpm) can be entered by: ? either setting the srwd bit after driving the write protect (w ) input pin low, ? or driving the write protect (w ) input pin low after setting the srwd bit. once the hardware-protected mode (hpm) has been entered, the only way of exiting it is to pull high the write protect ( w ) input pin. if the write protect ( w ) input pin is permanently tied high, the hardware-protected mode (hpm) can never be activated, and only th e software-protected mode (spm), using the block protect (bp1, bp0) bits in the status register, can be used. table 6. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protec t (bp1, bp0) bits of the status register. see table 2 . unprotected area (1) 10 software- protected (spm) status register is writable (if the wren instruction has set the wel bit). the values in the bp1 and bp0 bits can be changed. write-protected ready to accept write instructions 00 11 01 hardware- protected (hpm) status register is hardware write- protected. the values in the bp1 and bp0 bits cannot be changed. write-protected ready to accept write instructions
docid18203 rev 9 23/43 m95m02-dr instructions 42 6.5 read from memory array (read) as shown in figure 12 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). figure 12. read from memory array (read) sequence if chip select ( s ) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, a llowing the read cycle to be continued indefinitely. the whole memory can, ther efore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. c d ai13878 s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
instructions m95m02-dr 24/43 docid18203 rev 9 6.6 write to memo ry array (write) as shown in figure 13 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. the self-timed write cycle, tr iggered by the chip select ( s ) rising edge, continues for a period t w (as specified in ac characteristics in section 9: dc and ac parameters ), at the end of which the write in progress (wip) bit is reset to 0. figure 13. byte write (write) sequence in the case of figure 13 , chip select ( s ) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. however, if chip select ( s ) continues to be driven low, as shown in figure 14 , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the le ast significant bits of the internal address counter are incremented. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page. the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before), ? if a write cycle is already in progress, ? if the device has not been deselected, by driving high chip select (s ), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
docid18203 rev 9 25/43 m95m02-dr instructions 42 figure 14. page write (write) sequence 6.6.1 cycling with erro r correction code (ecc) m95m02-d devices offer an error correction code (ecc) logic. the ecc is an internal logic function which is transparent fo r the spi communication protocol. the ecc logic is implemented on ea ch group of four eeprom bytes (c) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on group s of four bytes, a single byte can be written/cycled independently. in this case, th e ecc function also writes/cycles the three other bytes located in the same group (c) . as a consequence, the ma ximum cycling budget is defined at group level and the cycling can be dist ributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in table 10 . -36 & ' 6 & ' 6 ,qvwuxfwlrq elwdgguhvv 'dwde\wh 'dwde\wh 'dwde\wh 'dwde\wh1 c. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
instructions m95m02-dr 26/43 docid18203 rev 9 6.7 read identification page (available only in m95m02-d devices) the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. reading this page is achieved with the read identification page instruction (see table 3 ). the chip select signal ( s ) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). address bit a10 must be 0, upper address bits are don't care, and the data byte pointed to by the lower address bits [a7:a0] is shifted out on serial data output (q). if chip select ( s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. the number of bytes to read in the id page must not exceed the page boundary, otherwise unexpected data is read (e.g.: when reading the id page from location 90d, the number of bytes should be less than or equal to 166d, as the id page boundary is 256 bytes). the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 15. read identification page sequence -36 # $ 3 1 (ighimpedance $ata/ut )nstruction bitaddress -3" -3" $ata/ut
docid18203 rev 9 27/43 m95m02-dr instructions 42 6.8 write identification page the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. writing this page is achieved with the write identification page instruction (see table 3 ). the chip select signal ( s ) is first driven low. the bits of the instruction byte, address bytes, and at least one data byte are then shifted in on serial data input (d). address bit a10 must be 0, upper address bits are don't care, the lower address bits [a7:a0] address bits define the byte address inside the identification page. the instruction sequence is shown in figure 16 . figure 16. write identification page sequence -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
instructions m95m02-dr 28/43 docid18203 rev 9 6.9 read lock status (availabl e only in m95m02-d devices) the read lock status instruction (see table 3 ) is used to check whether the identification page is locked or not in read-only mode. th e read lock status sequence is defined with the chip select ( s ) first driven low. the bits of the instruction byte and address bytes are then shifted in on serial data input (d). address bit a10 must be 1, all other address bits are don't care. the lock bit is the lsb (least signifi cant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select ( s ) continues to be driven low, the same data byte is shifted out. the read cycle is terminated by driving chip select ( s ) high. the instruction sequence is shown in figure below. figure 17. read lock status sequence -36 # $ 3 1 (ighimpedance $ata/ut )nstruction bitaddress -3" -3" $ata/ut
docid18203 rev 9 29/43 m95m02-dr instructions 42 6.10 lock id the lock id instruction permanently locks the identification page in read-only mode. before this instruction can be accepted, a write enable (wren) instruction must have been executed. the lock id instruction is is sued by driving chip select ( s ) low, sending the instruction code, the address and a data byte on serial data input (d), and driving chip select ( s ) high. in the address sent, a10 must be equal to 1, all other address bits are don't care. the data byte sent must be equal to the binary value xxxx xx1x, wher e x = don't care. chip select ( s ) must be driven high after the rising ed ge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the lock id instruction is not executed. driving chip select ( s ) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is t w (as specified in ac characteristics in section 9: dc and ac parameters ). the instruction se quence is shown in figure 18 . the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress, ? if the block protect bits (bp1,bp0) = (1,1), ? if a rising edge on chip select (s ) happens outside of a byte boundary. figure 18. lock id sequence -36 # $ 3 1 (ighimpedance )nstruction bitaddress $atabyte
power-up and delivery state m95m02-dr 30/43 docid18203 rev 9 7 power-up and delivery state 7.1 power-up state after power-up, the device is in the following state: ? standby power mode, ? deselected (after power-up, a falling ed ge is required on chip select (s ) before any instructions can be started), ? not in the hold condition, ? the write enable latch (wel) is reset to 0, ? write in progress (wip) is reset to 0. the srwd, bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 initial delivery state the device is delivered with the memory array bi ts and identification page bits set to all 1s (each byte = ffh). the status register write disable (srwd) and block protect (bp1 and bp0) bits are initialized to 0.
docid18203 rev 9 31/43 m95m02-dr maximum rating 42 8 maximum rating stressing the device outside the ratings listed in table 7 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small bod y, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european directive on rest rictions of hazardous substances (rohs) 2011/65/eu. c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v i ol dc output current (q = 0) - 5 ma i oh dc output current (q = 1) - 5 ma v esd electrostatic discharge voltage (human body model) (2) 2. positive and negative pulses applied on different co mbinations of pin connec tions, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 , r2=500 ). - 3000 v
dc and ac parameters m95m02-dr 32/43 docid18203 rev 9 9 dc and ac parameters this section summarizes the operating condi tions and the dc/ac characteristics of the device. figure 19. ac measurement i/o waveform table 8. operating conditions (m95m02-dr, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 9. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times - 25 ns input pulse voltages 0.2 v cc to 0.8 v cc v input and output timing reference voltages 0.3 v cc to 0.7 v cc v !)# 6 ## 6 ## 6 ## 6 ## )nputandoutput timingreferencelevels )nputvoltagelevels
docid18203 rev 9 33/43 m95m02-dr dc and ac parameters 42 table 10. cycling performance by groups of four bytes symbol parameter test conditions min. max. unit ncycle write cycle endurance (1) 1. the write cycle endurance is defined for groups of fo ur data bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. the write cycle endurance is defined by characterization and qualification. ta 25 c, v cc (min) < v cc < v cc (max) - 4,000,000 write cycle (2) 2. a write cycle is executed when either a page write, a byte write, a wrsr, a wrid or an lid instruction is decoded. when using the byte write, the page writ e or the wrid instruction, refer also to section 6.6.1: cycling with error correction code (ecc) . ta = 85 c, v cc (min) < v cc < v cc (max) - 1,200,000 table 11. memory cell data retention parameter test conditions min. unit data retention (1) 1. the data retention behavior is checked in producti on, while the 200-year limit is defined from characterization and qualification results. ta = 55 c 200 year table 12. capacitance symbol parameter test conditions (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 5 mhz. min. max. unit c out output capacitance (q) v out = 0 v - 8 pf c in input capacitance (d) v in = 0 v - 8 pf input capacitance (other pins) v in = 0 v - 6 pf
dc and ac parameters m95m02-dr 34/43 docid18203 rev 9 table 13. dc characteristics symbol parameter test conditions min max unit i li input leakage current v in = v ss or v cc - 2a i lo output leakage current s = v cc , v out = v ss or v cc - 2a i cc supply current (read) c = 0.1 v cc /0.9 v cc at 5 mhz, 1.8 v v cc < 5.5 v, q = open -3ma i cc0 (1) supply current (write) during t w , s = v cc ,-3ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , v cc = 1.8 v -3a s = v cc , v in = v ss or v cc , 1.8 v v cc < 2.5 v -5a s = v cc , v in = v ss or v cc , 2.5 v v cc < 5.5 v -5a v il input low voltage 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc 5.5 v ?0.45 0.3 v cc v ih input high voltage 1.8 v v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc 5.5 v 0.7 v cc v cc +1 v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v - 0.3 v v cc = 2.5 v, i ol = 1.5 ma or v cc = 5 v, i ol = 2 ma -0.4v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v 0.8 v cc -v v cc = 2.5 v, i oh = ?0.4 ma or v cc = 5 v, i oh = -2 ma 1. characterized value, not tested in production.
docid18203 rev 9 35/43 m95m02-dr dc and ac parameters 42 table 14. ac characteristics test conditions specified in table 9 and table 11 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 60 - ns t shch t css2 s not active setup time 60 - ns t shsl t cs s deselect time 90 - ns t chsh t csh s active hold time 60 - ns t chsl s not active hold time 60 - ns t ch (1) 1. t ch + t cl must never be lower than the shortest possible clock period, 1/f c (max). t clh clock high time 90 - ns t cl (1) t cll clock low time 90 - ns t clch (2) 2. characterized only, not tested in production. t rc clock rise time - 2 s t chcl (2) t fc clock fall time - 2 s t dvch t dsu data in setup time 20 - ns t chdx t dh data in hold time 20 - ns t hhch clock low hold time after hold not active 60 - ns t hlch clock low hold time after hold active 60 - ns t clhl clock low set-up time before hold active 0 - ns t clhh clock low set-up time before hold not active 0-ns t shqz (2) t dis output disable time - 80 ns t clqv t v clock low to output valid - 80 ns t clqx t ho output hold time 0 - ns t qlqh (2) t ro output rise time - 80 ns t qhql (2) t fo output fall time - 80 ns t hhqv t lz hold high to output valid - 80 ns t hlqz (2) t hz hold low to output high-z - 80 ns t w t wc write time - 10 ms
dc and ac parameters m95m02-dr 36/43 docid18203 rev 9 figure 20. serial input timing figure 21. hold timing figure 22. serial output timing # $ !)d 3 -3"). 1 t$6#( (ighimpedance ,3"). t3,#( t#($8 t#,#( t3(#( t3(3, t#(3( t#(3, t#( t#, t#(#, # 1 !)c 3 1 t#,(, t(,#( t((#( t#,(( t((16 t(,1: # 1 !)f 3 $ !$$2 ,3"). t3(1: t#( t#, t1,1( t1(1, t#(#, t#,18 t#,16 t3(3, t#,#(
docid18203 rev 9 37/43 m95m02-dr package mechanical data 42 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 23. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 15. so8n ? 8-lead plastic small outli ne, 150 mils body width, mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a - - 1.750 - - 0.0689 a1 - 0.100 0.250 - 0.0039 0.0098 a2 - 1.250 - - 0.0492 - b - 0.280 0.480 - 0.0110 0.0189 c - 0.170 0.230 - 0.0067 0.0091 ccc - - 0.100 - - 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h - 0.250 0.500 - 0.0098 0.0197 k-08-08 l - 0.400 1.270 - 0.0157 0.0500 l1 1.040 - - 0.0409 - - 62$ ( fff e h $ ' f ( k[? $ n pp / / $ *$8*(3/$1(
package mechanical data m95m02-dr 38/43 docid18203 rev 9 figure 24. m95m02-drcs6tp/k, wlcsp standard package outline, bump side view 1. drawing is not to scale. table 16. m95m02-drcs6tp/k, wlcsp package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. min typ max min typ max a 0.540 0.500 0.580 0.0213 0.0197 0.0228 a1 0.190 - - 0.0075 - - a2 0.350 - - 0.0138 - - b (bump diameter) 0.270 - - 0.0106 - - d 3.536 3.556 3.576 0.1392 0.1400 0.1408 e 1.991 2.011 2.031 0.0784 0.0792 0.0800 e - 0.500 - - 0.0197 - e1 - 2.100 - - 0.0827 - e2 - 1.000 - - 0.0394 - e3 - 1.400 - - 0.0551 - 3ideview "umpside ! ! $ e e e % e -36 !
docid18203 rev 9 39/43 m95m02-dr package mechanical data 42 figure 25. wlcsp 8-bump wafer lenght chip-scale recommended land pattern 069 h h h h
part numbering m95m02-dr 40/43 docid18203 rev 9 11 part numbering table 17. ordering information scheme example: m95m02-d r mn 6 t p \k device type m95 = spi serial access eeprom device function m02-d = 2048 kbit plus identification page operating voltage r = v cc = 1.8 to 5.5 v package (1) 1. all packages are ecopack2? (r ohs compliant and halogen-free). mn = so8 (150 mil width) cs = standard wlcsp device grade 6 = industrial temperature range, ?40 to 85 c device tested with standard test flow option t = tape and reel packing blank = tube packing plating technology p = rohs compliant and halogen-free (ecopack?) process (2) 2. the process letters apply to wlcsp devices only . the process letters appear on the device package (marking) and on the shipment box. please contact your nearest st sales office for further information. /k = manufacturing technology code
docid18203 rev 9 41/43 m95m02-dr revision history 42 12 revision history table 18. document revision history date revision changes 15-nov-2010 1 initial release. 10-dec-2010 2 updated dc and ac characteristics according to characterization test results. 10-jan-2011 3 updated ordering information. 10-may-2011 4 updated table 13: ac characteristics and related text, and table 12: dc characteristics . 19-oct-2011 5 changed datasheet status to full datasheet. modified section 1: description . added figure 3: wlscp connections (bump side view) . updated figure 4: bus master and memory devices on the spi bus and figure 7: block diagram . modified section 7: ecc (error corre ction code) and write cycling . updated note 2 in table 7: absolute maximum ratings . added table 8: memory cell characteristics . updated figure 24: m95m02-dr wlcsp package outline and table 15: m95m02-dr wlcsp package mechanical data . updated disclaimer on last page. 04-oct-2012 6 text and structure of document modified as per new m95xxx standard eeprom datasheet template. updated: ? cycling: 4 million cycles ? data retention: 200 years added: ? standard wlcsp (cs) 19-dec-2012 7 updated section 7.2: initial delivery state . restored figure 23 , figure 24 and figure 25 .
revision history m95m02-dr 42/43 docid18203 rev 9 13-mar-2013 8 document reformatted. replaced ?ball? by ?bump? in the entire document. deleted figure 3: thin wlcsp connections (bump side view) , figure 24: m95m02-dr thin wlcsp package (ct) outline, bump side view and table 15: m95m02-dr thin wlcsp package mechanical data . renamed figure 24: m95m02-drcs6tp/k, wlcsp standard package outline, bump side view and table 16: m95m02-drcs6tp/k, wlcsp package mechanical data updated package information in table 17: ordering information scheme . 15-sep-2014 9 updated wlcsp (cs) package figure on cover page. removed ?preliminary data? footnote from figure 3 , figure 24 and table 16 . removed note about exposure to uv light in section 1: description . updated table 3: instruction set , and removed footnotes from it. added table 4: significant bits within the address bytes and figure 25: wlcsp 8-bump wafer lenght chip-scale recommended land pattern . updated note 1 in table 7: absolute maximum ratings . updated table 14: ac characteristics and table 17: ordering information scheme . table 18. document revision history (continued) date revision changes
docid18203 rev 9 43/43 m95m02-dr 43 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of M95M02-DRCS6TPK

	To Download M95M02-DRCS6TPK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .